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Lattice Semiconductor
Functional Description
The DA, SA, L/T, and DATA fields are derived from higher applications through the FIFO interface and then encap-
sulated into an Un-tagged Ethernet frame. This frame is not sent over the network until the network has been idle
for a minimum of Inter-Packet Gap (IPG) time. The Frame encapsulation consists of adding the Preamble bits, the
Start of Frame Data (SFD) bits and the CRC check sum to the end of the frame (FCS). If padding is not disabled, all
short frames are padded with hexadecimal 00.
The input signal tx_fifoeof is asserted along with the last set of data transfer to indicate the end of the frame. The
Tx MAC requires a continuous stream of data for the entire frame. There cannot be any bubbles of “no data trans-
fer” within a frame. If the MAC is able to transmit the frame without any errors, the tx_done signal is asserted. Once
the transmission has ended, data on the tx_stat_vector bus is presented to the host, including all the statistical
information collected in the process of transmitting the frame. Data on this bus is qualified by assertion of the
tx_staten signal.
After the Transmit MAC is done transmitting a frame, it waits for more frames from the FIFO interface. During this
time, it goes to an idle state that can be detected by reading the TX_RX_STS register. Since the MODE register
can be written at any time, the Tx MAC can be disabled while it is actively transmitting a frame. In such cases, the
MAC will completely transmit the current frame and then return to the idle state. The control registers should be
programmed only after the MAC has returned to the IDLE state.
External Transmit FIFO
The interface between the Tx MAC and the external, client side FIFO is eight bits wide. The bit presented on posi-
tion 0 is transmitted first and the bit in position 7 is transmitted last. In other words, bit[0] will be transmitted on the
txd[0] signal of GMII while the bit[7] will be transmitted on txd[7].
Logic inside the MAC signals if the frame ready for transmission at the head of the FIFO is a Control frame. This is
done so the Tx MAC can continue transmission of a Control frame while it is paused.
FIFO Under-flow
If a FIFO underflow occurs, the FIFO logic must assert tx_fifoempty. If at least 64 bytes have been transmitted, the
Tx MAC aborts the transmission by asserting tx_er. In addition, the Tx MAC inserts erroneous CRC bits into the
packet to guarantee the receiver will detect the error in the packet. If less than 64 bytes have been transmitted
when the FIFO underflow occurs, the MAC will pad the remaining bytes before ending the transmission. In either
case, the MAC asserts tx_discfrm indicating an error during transmission.
Transmitting PAUSE Frame
Two different methods are used for transmitting a PAUSE frame. In the first method, the application layer forms a
PAUSE frame and submits it for transmission via the FIFO. In the other method, the application layer signals the Tx
MAC directly to transmit a PAUSE frame. This is accomplished by asserting tx_sndpausreq. In this case the Tx
MAC will complete transmission of the current packet and then transmit a PAUSE frame with the PAUSE time value
supplied through the tx_sndpaustim bus.
Retries on Collision
When operating in the half-duplex mode, the Transmit MAC has the capability to perform re-transmission of frames
that have experienced in-window collision up to the specified maximum. This is possible because the MAC always
buffers the first 64 bytes of the frame.
If the MAC has been disabled while it is backing off (soon after a collision), it will only return to the IDLE state after
it has successfully transmitted the frame or has exceeded the retry limit.
In the 10/100 mode, the Tx MAC provides the following information:
? Whether the frame deferred before transmission
? The number of times the frame experiences collision before transmission.
This information is sent as a part of the statistics vector. For a frame transmitted without any errors, the statistics
vector, qualified by the enable signal, is asserted along with the tx_done signal.
IPUG51_03.0, December 2010
23
Tri-Speed Ethernet MAC User’s Guide
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